Posted by Shannon Hilbert in Verilog / VHDL on 2-4-13

Verilog hdl 2nd_edition_samir_palnitkar - SlideShare

Verilog Hdl Synthesis: A Practical Primer: J

The Quartus II software supports the following Verilog HDL language directives, which you can use in a to direct the Logic Synthesizer to perform or not perform certain actions when synthesizing a design:

Free verilog hdl synthesis a practical primer PDF

Well it is a long story; let me cover that in the synthesis part of Verilog tutorial. You can refer to Actel HDL coding Style. One simple logic is: any code inside always blocks with edge sensitive sensitivity list, results in flip-flops and assign; inside level sensitive always blocks results in combo logic.

Rev 1.0Jan 2005  SNUG 2004(Boston)SystemVerilog 2-State Simulation Performance & Verification AdvantagesRev 1.0Sep 2004  SNUG 2003(Boston)SystemVerilog - Is This The Merging of Verilog & VHDL?